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10-bit, 65/80/105 msps, 3 v a/d converter data sheet ad9215 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no re- sponsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2003C2013 analog devices, inc. all rights reserved. technical support www.analog.com features single 3 v supply operation (2.7 v to 3.3 v) snr = 58 dbc (to nyquist) sfdr = 77 dbc (to nyquist) low power adc core: 96 mw at 65 msps, 104 mw @ 80 msps, 120 mw at 105 msps differential input with 300 mhz bandwidth on-chip reference and sample-and-hold amplifier dnl = 0.25 lsb flexible analog input: 1 v p-p to 2 v p-p range offset binary or twos complement data format clock duty cycle stabilizer applications ultrasound equipment if sampling in communications receivers battery-powered instruments hand-held scopemeters low cost digital oscilloscopes functional block diagram sha vin+ vin? reft refb drvdd clk pdwn mode clock duty cycle stablizer mode select dgnd or d9 (msb) 02874-a-001 d0 avdd correction logic output buffers 10 ref select agnd 0.5v vref sense ad9215 pipeline adc core figure 1. product description the ad9215 is a family of monolithic, single 3 v supply, 10-bit, 65/80/105 msps analog-to-digital converters (adc). this family features a high performance sample-and-hold amplifier (sha) and voltage reference. the ad9215 uses a multistage differential pipelined architecture with output error correction logic to pro- vide 10-bit accuracy at 105 msps data rates and to guarantee no missing codes over the full operating temperature range. the wide bandwidth, truly differential sample-and-hold ampli- fier (sha) allows for a variety of user-selectable input ranges and offsets including single-ended applications. it is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the nyquist rate. combined with pow- er and cost savings over previously available adcs, the ad9215 is suitable for applications in communications, imaging, and medical ultrasound. a single-ended clock input is used to control all internal conversion cycles. a duty cycle stabilizer compensates for wide variations in the clock duty cycle while maintaining excellent performance. the digital output data is presented in straight binary or twos complement for- mats. an out-of-range signal indicates an overflow condition, which can be used with the msb to determine low or high overflow. fabricated on an advanced cmos process, the ad9215 is avail- able in both a 28-lead surface-mount plastic package and a 32-lead chip scale package and is specified over the industrial temperature range of ?40c to +85c. product highlights 1. the ad9215 operates from a single 3 v power supply and features a separate digital output driver supply to accom- modate 2.5 v and 3.3 v logic families. 2. operating at 105 msps, the ad9215 core adc consumes a low 120 mw; at 80 msps, the power dissipation is 104 mw; and at 65 msps, the power dissipation is 96 mw. 3. the patented sha input maintains excellent performance for input frequencies up to 200 mhz and can be config- ured for single-ended or differential operation. 4. the ad9215 is part of several pin compatible 10-, 12-, and 14-bit low power adcs. this allows a simplified upgrade from 10 bits to 12 bits for systems up to 80 msps. 5. the clock duty cycle stabilizer maintains converter per- formance over a wide range of clock pulse widths. 6. the out of range (or) output bit indicates when the signal is beyond the selected input range.
ad9215 data sheet rev. b | page 2 of 36 table of contents specifications ..................................................................................... 3 absolute maximum ratings 1 .......................................................... 6 explanation of test levels ........................................................... 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 equivalent circuits ....................................................................... 8 definitions of specifications ....................................................... 8 typical performance characteristics ........................................... 10 applying the ad9215 theory of operation ............................... 14 clock input and considerations .............................................. 15 evaluation board ........................................................................ 18 outline dimensions ....................................................................... 33 ordering guide ........................................................................... 34 revision his tory 2/13 data sheet changed from a rev. a to a rev. b changes to figure 4 and added epad note to pin configur a- tions and function descriptions section ..................................... 7 changes to voltage reference section ........................................ 17 changes to evaluation board section ......................................... 18 updated outline dimensio ns ...................................................... 33 changes to ordering guide ......................................................... 34 2 /04 data sheet changed from a rev. 0 to a rev. a renumbered figures and tables .............................. universal changes to product title ................................................................ 1 chang e s to features ........................................................................ 1 changes to product description ................................................... 1 changes to product highlights ..................................................... 1 changes to specif ications ............................................................... 2 changes to figure 2 ......................................................................... 4 changes to figures 9 to 11 ........................................................... 10 added figure 14 ............................................................................ 10 adde d figures 16 and 18 .............................................................. 11 changes to figures 21 to 24 and 25 to 26 ................................... 12 deleted figure 25 ........................................................................... 12 changes to figures 2 8 and 29 ...................................................... 13 changes to f igure 3 1 ..................................................................... 14 changes t0 figure 3 5 ..................................................................... 16 ch anges to figures 5 0 through 5 8............................................... 26 added table 11 .............................................................................. 31 updated outline dimensions ...................................................... 32 changes to ordering guide ......................................................... 33 5/03 revision 0: initial version
data sheet ad9215 rev. b | page 3 of 36 specifications avdd = 3 v, drvdd = 2.5 v, specified maximum conversion rat e, 2 v p - p differential in put, 1.0 v internal refer ence, unless ot h erwise noted. table 1 . dc specifications ad9215bru - 65/ ad9215bcp - 65 ad9215bru - 80/ ad9215bcp - 80 ad9215bru - 105/ ad9215bcp - 105 parameter temp test level min typ max min typ max min ty p max unit resolution full vi 10 10 10 bits accuracy no missing codes full vi guaranteed guaranteed guaranteed offset error 1 full vi 0.3 2.0 0.3 2.0 0.3 2.0 % fsr gain error 1 full vi 0 +1.5 +4.0 +1.5 +4.0 +1.5 +4.0 % fsr differential nonlinearity (dnl) 2 full vi ? 1.0 0.5 +1.0 ? 1.0 0.5 +1.0 ? 1.0 0.6 +1.2 lsb integral nonlinearity (inl) 2 full vi 0.5 1.2 0.5 1.2 0.65 1.2 lsb temperature drift offset error 1 full v +15 +15 +15 ppm/c gain error 1 full v +30 +30 +30 ppm/c reference voltage (1 v mode) full v 230 230 230 ppm/c internal voltage reference output voltage error (1 v mode) full vi 2 35 2 35 2 35 mv load regulation @ 1.0 ma full v 0.2 0.2 0.2 mv output voltage error (0.5 v mode) full v 1 1 1 mv load regulation @ 0.5 ma full v 0.2 0.2 0.2 mv input referred noise vref = 0.5 v 25c v 0.8 0.8 0.8 lsb rms vref = 1.0 v 25c v 0.4 0.4 0.4 lsb rms analog input input span, vref = 0.5 v full iv 1 1 1 v p -p input span, vref = 1.0 v full iv 2 2 2 v p -p input capacitance 3 full v 2 2 2 pf reference input resistance f ull v 7 7 7 k? power supplies supply voltage avdd full iv 2.7 3.0 3.3 2.7 3.0 3.3 2.7 3.0 3.3 v drvdd full iv 2.25 2.5 3.6 2.25 2.5 3.6 2.25 2.5 3.6 v supply current i avdd 2 full vi 32 35 34.5 39 40 44 ma i drvdd 2 25c v 7.0 8.6 1 1.3 ma psrr full v 0.1 0.1 0.1 % fsr power consumption sine wave input 2 i avdd 2 full vi 96 10 4 120 mw i drvdd 2 25c v 18 20 25 mw stan dby power 4 25c v 1.0 1.0 1.0 mw 1 with a 1.0 v internal reference. 2 measured at f in = 2.4 mhz, full - scale sine wave, with approximately 5 pf loading on each output bit. 3 input capacitance refers to the effective capacitance between one differential input pin and agnd. refer to figure 5 for the equivalent analog input stru c ture. 4 standby power is measured with a dc input, the clk pin inactive (i.e., set to avdd or agnd).
ad9215 data sheet rev. b | page 4 of 36 avdd = 3 v, drvdd = 2.5 v, specified maximum conversion rate , 2 v p-p differential input, 1.0 v internal reference, ain = ?0.5 dbfs, mode = avdd/3 (duty cycle stabilizer [dcs] enabled), unless otherwise noted. table 2. ac specifications ad9215bru-65/ ad9215bcp-65 ad9215bru-80/ ad9215bcp-80 ad9215bru-105/ ad9215bcp-105 parameter temp test level min typ max min typ max min typ max unit signal-to-noise ratio (snr) f in = 2.4 mhz full vi 56.0 58.5 56.0 58.5 57.5 db 25c i 57.0 59.0 57.0 59.0 56.6 58.5 db f in = nyquist 1 full vi 56.0 58.0 56.0 58.0 57.5 db 25c i 56.5 58.5 56.5 58.5 56.4 58.0 db f in = 70 mhz 25c v 58.0 57.8 db f in = 100 mhz 25c v 57.5 57.7 db signal-to-noise and distortion (sinad) f in = 2.4 mhz full vi 55.8 58.5 55.7 58.5 57.6 db 25c i 56.5 59.0 56.8 58.5 56.5 58.2 db f in = nyquist 1 full vi 55.8 58.0 55.5 58.0 57.3 db 25c i 56.3 58.5 56.3 58.5 56.1 57.8 db f in = 70 mhz 25c v 56.0 57.7 db f in = 100 mhz 25c v 55.5 57.4 db effective number of bits (enob) f in = 2.4 mhz full vi 9.1 9.5 9.0 9.5 9.3 bits 25c i 9.2 9.6 9.3 9.5 9.2 9.5 bits f in = nyquist 1 full vi 9.1 9.4 9.0 9.4 9.4 bits 25c i 9.1 9.5 9.0 9.5 9.1 9.4 bits f in = 70 mhz 25c v 9.1 9.4 bits f in = 100 mhz 25c v 9.0 9.3 bits worst harmonic (second or third) f in = 2.4 mhz full vi ?78 ?64 ?78 ?64 ?78 dbc 25c i ?80 ?65 ?80 ?65 ?84 ?70 dbc f in = nyquist 1 full vi ?77 ?64 ?76 ?63 ?74 dbc 25c i ?78 ?65 ?78 ?65 ?75 ?61 dbc f in = 70 mhz 25c v ?70 ?75 dbc f in = 100 mhz 25c v ?70 ?74 dbc worst other (excluding second or third) f in = 2.4 mhz full vi ?77 ?67 ?77 ?66 ?73 dbc 25c i ?78 ?68 ?77 ?68 ?75 ?66 dbc f in = nyquist 1 full vi ?77 ?67 ?77 ?66 ?71 dbc 25c i ?78 ?68 ?77 ?68 ?75 ?63 dbc f in = 70 mhz 25c v ?80 -75 dbc f in = 100 mhz 25c v ?80 ?75 dbc two-tone sfdr (ain = C7 dbfs) f in1 = 70.3 mhz, f in2 = 71.3 mhz 25c v 75 75 dbc f in1 = 100.3 mhz, f in2 = 101.3 mhz 25c v 74 74 dbc analog bandwidth 25c v 300 300 300 mhz 1 tested at f in = 35 mhz for ad9215-65; f in = 39 mhz for ad9215-80; and f in = 50 mhz for ad9215-105.
data sheet ad9215 rev. b | page 5 of 36 table 3 . digital specifications ad9215bru - 65/ ad92 15bcp - 65 ad9215bru - 80/ ad9215bcp - 80 ad9215bru - 105/ ad9215bcp - 105 parameter temp test level min typ max min typ max min typ max unit logic inputs (clk, pdwn) high level input voltage full iv 2.0 2.0 2.0 v low l evel input voltage full iv 0.8 0.8 0.8 v high level input current full iv ?650 +10 ?650 +10 ?650 +10 a low level input current full iv ?70 +10 ?70 +10 ?70 +10 a input capacitance full v 2 2 2 pf logic outputs 1 drvdd = 2 .5 v high level output voltage full iv 2.45 2.45 2.45 v low level output voltage full iv 0.05 0.05 0.05 v 1 output voltage levels measured with a 5 pf load on each output. table 4 . switching specifications ad9215bru - 65/ ad9215bcp - 65 ad9215bru - 80/ ad9215bcp - 80 ad9215bru - 105/ ad9215bcp - 105 parameter temp test level min typ max min typ max min typ max unit clock input parameters maximum conversion rate full vi 65 80 105 msps minimum conversion rate ful l v 5 5 5 msps clock period full v 15.4 12.5 9.5 ns data output parameters output delay 1 (t od ) full vi 2.5 4.8 6.5 2.5 4.8 6.5 2.5 4.8 6.5 ns pipeline delay (latency) full v 5 5 5 cycles aperture delay 25c v 2.4 2.4 2.4 ns aperture uncertainty (jitter) 25c v 0.5 0.5 0.5 ps rms wake - up time 2 25c v 7 7 7 ms out -of - range recovery time 25c v 1 1 1 cycles 02874-a-002 t a t pd n?7 n?6 n?5 n?4 n?3 n?2 n?1 n n+1 n+2 analog input clk data out n?1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 f igure 2 . timing diagram 1 output delay is measured from clk 50% transition to data 50% transition, with 5 pf load on each output. 2 wake - up time is dependent on the value of decoupling capacitors; typical values shown with 0.1 f and 10 f capacitors on reft and refb.
ad9215 data sheet rev. b | page 6 of 36 absolute maximum rat ings 1 table 5. mnemonic with respect to min max unit electrical avdd agnd ?0.3 +3.9 v drvdd drgnd ?0.3 +3.9 v agnd drgnd ?0.3 +0.3 v avdd drvdd ?3.9 +3.9 v digital outputs drgnd ?0.3 drvdd + 0.3 v clk, mode agnd ?0.3 avdd + 0.3 v vin+, vin? agnd ?0.3 avdd + 0.3 v vref agnd ?0.3 avdd + 0.3 v sense agnd ?0.3 avdd + 0.3 v refb, reft agnd ?0.3 av dd + 0.3 v pdwn agnd ?0.3 avdd + 0.3 v environmental 2 operating temperature junction temperature lead temperature (10 sec) storage temperature ?40 +85 c 150 c 300 c ?65 +150 c notes 1 absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily i m plied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 typical thermal impedances 28 - lead tssop: ja = 67.7c/w, 32 - lead lfcsp: ja = 32.7c/w; heat sink soldered down to ground plane. explanation of test levels test level i 100% production tested. ii 100% production tested at 25c and sample tested at spe c- i fied temperatures. iii sample tested only. iv parameter is guaranteed by design and characterizatio n testing. v parameter is a typical value only. vi 100% production tested at 25c; guaranteed by design and characterization testing for industrial tempe rature range; 100% production tested at temperature extremes for mil i- tary devices. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can dis charge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance d egradation or loss of functionality.
data sheet ad9215 rev. b | page 7 of 36 pin configurations and function descriptions 02874-a-003 1 2 3 4 5 6 7 8 9 10 11 12 13 14 or mode sense vref refb reft avdd agnd vin+ vin? agnd avdd clk pdwn d9 (msb) d8 d7 d6 drvdd drgnd d5 d4 d3 d2 d1 d0 (lsb) dnc 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ad9215 top view (not to scale) dnc = do not connect dnc figure 3. tssop (ru-28) 0 2874-a-004 19 17 20 21 18 14 13 12 11 10 9 15 16 d5 d 4 d3 d2 d1 (lsb) d0 drgnd drvdd 32 31 30 29 28 27 26 25 a vdd agn d vin? vin+ agn d avdd reft refb 22 23 24 d8 d6 d9 (msb) or d7 mode sense vref 1 2 3 4 5 6 7 8 dnc clk dnc pdwn dnc dnc dnc dnc ad9215 top view (not to scale) notes 1. dnc = do not connect. 2. it is recommended that the exposed pad be soldered to the ground plane for the lfcsp package. there is an increased reliability of the solder joints, and the maximum thermal capability of the package is achieved with the exposed pad soldered to the customer board. figure 4. lfcsp (cp-32-7) table 6. pin function descriptions tssop pin no. lfcsp pin no. mnemonic description 1 21 or out-of-range indicator. 2 22 mode data format and clock duty cycle stabilizer (dcs) mode selection. 3 23 sense reference mode selection. 4 24 vref voltage reference input/output. 5 25 refb differential reference (negative). 6 26 reft differential reference (positive). 7, 12 27, 32 avdd analog power supply. 8, 11 28, 31 agnd analog ground. 9 29 vin+ analog input pin (+). 10 30 vin? analog input pin (?). 13 2 clk clock input pin. 14 4 pdwn power-down function selection (active high). 15 to 16 1, 3, 5 to 8 dnc do not connect, recommend floating this pin. 17 to 22, 25 to 28 9 to 14, 17 to 20 d0 (lsb) to d9 (msb) data output bits. 23 15 drgnd digital output ground. 24 16 drvdd digital output driver supply. must be decoupled to drgnd with a minimum 0.1 f capacitor. recommended decoupling is 0.1 f in parallel with 10 f. n/a 33 ep exposed pad. it is recommended that the ex posed pad be soldered to the ground plane for the lfcsp package. there is an increase d reliability of the solder joints, and the maximum thermal capability of the package is achieved with the exposed pad soldered to the customer board.
ad9215 data sheet rev. b | page 8 of 36 equivalent circuits 02874-a-005 avdd mode figure 5 . equivalent analog input circuit 02874-a-006 avdd mode 20k? figure 6 . equivalent mode input circuit 02874-a-007 d9?d0, or drvdd figure 7 . equivalent digital output circuit 02874-a-008 2.6k? 2.6k? avdd clk figure 8 . equivalent digital input circuit definitions of speci fications aperture delay aperture delay is a measure of the sample - and - hold amplifier (sha) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. aperture jitter aperture jitter is the variation in aperture delay for successive samples and can be manifested as frequency - dependent noise on the input to the adc. clock pulse w idth and duty cycle pulse width high is the minimum amount of time that the clock pulse should be left in the logic 1 state to achieve rated perfo r- mance. pulse width low is the minimum time the clock pulse should be left in the low state. at a given clock rate, these spec i- fications define an accepta ble clock duty cycle. differential nonlinearity (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guara n teed no missing codes to 10 - bit resolution indicate that all 1024 codes, respectively, must be present over all operating ranges. effective number of bits (enob) for a sine wave, sinad can be expressed in terms of the nu m- ber of bits. using the following formula , it is possible to obtain a measure of performance expresse d as n , the effective number of bits n = ( sinad C 1.76)/6.02 thus, the effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured sinad. gain error the first code transition should occ ur at an analog value 1/2 lsb above negative full scale. the last transition should occur at an analog value 1 1/2 lsb below the positive full scale. gain error is the deviation of the actual difference between the first and last code transitions and the i deal difference between the first and last code transitions. integral nonlinearity (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale o ccurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is mea s ured from the middle of each particular code to the true straight line. maximum conversion rate the cl ock rate at which parametric testing is performed. minimum conversion rate the clock rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. offset error the major carry transition should occur for an analog value 1/2 lsb below vin+ = vin?. zero error is defined as the devi a tion of the actual transition from that point. out - of - range recovery time out - of - range recovery time is the time it takes for the adc to reacquire the analog input after a transient from 10% above positive fu ll scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. output propagation delay the delay between the clock logic threshold and the time when all bits are within valid logic levels. power supply r ejection the specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value
data sheet ad9215 rev. b | page 9 of 36 with the supply at its maximum limit. signal - to - noise and distortion (sinad) ratio sinad is the ratio of the rms value of the measured input si g- nal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. signal - to - noise ratio (snr) snr is the ratio of the rms value of the mea sured input signal to the rms sum of all other spectral components below the n y quist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. spurious - free dynamic range (sfdr) sfdr is the difference in db betwee n the rms amplitude of the input signal and the peak spurious signal. temperature drift the temperature drift for zero error and gain error specifies the maximum change from the initial (25c) value to the value at t min or t max . total harmonic distortion ( thd) thd is the ratio of the rms sum of the first six harmonic co m- ponents to the rms value of the measured input signal and is expressed as a percentage or in decibels. two - tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. it may be reported in dbc (i.e., degrades as signal levels are lowered) or in dbfs (a l ways related back to converter full scale).
ad9215 data sheet rev. b | page 10 of 36 typical performance characteristics avd d = 3.0 v, drvdd = 2.5 v with dcs e nabled, t a = 25c, 2 v differential i nput, a in = ?0.5 dbfs, vref = 1.0 v, unless otherwise noted. 02874-a-062 ?120 0 ?20 ?40 ?60 ?80 ?100 0 52.50 45.94 39.38 32.81 26.25 19.69 13.13 6.56 amplitude (dbfs) frequency (mhz) a in = ?0.5dbfs snr = 58.0 enob = 9.4 bits sfdr = 75.5db figure 9 . single - tone 32k fft with f in = 10.3 mhz, f sample = 105 msps 02874-a-063 ?120 0 ?20 ?40 ?60 ?80 ?100 0 52.50 45.94 39.38 32.81 26.25 19.69 13.13 6.56 amplitude (dbfs) frequency (mhz) a in = ?0.5dbfs snr = 57.8 enob = 9.4 bits sfdr = 75.0db figure 10 . single - tone 32k fft with f in = 70.3 mhz, f sample = 105 msps 02874-a-065 ?120 0 ?20 ?40 ?60 ?80 ?100 0 52.50 45.94 39.38 32.81 26.25 19.69 13.13 6.56 amplitude (dbfs) frequency (mhz) a in = ?0.5dbfs snr = 57.7 enob = 9.3 bits sfdr = 75db figu re 11 . single - tone 32k fft with f in = 100.3 mhz, f sample = 105 msps 02874-a-012 encode (msps) db 70 75 80 65 60 55 50 5 15 25 35 45 55 65 75 85 ain = ?0.5dbfs 1v p-p sfdr (dbc) 2v p-p sfdr (dbc) 1v p-p snr (db) 2v p-p snr (db) figure 12 . ad9215 - 80 snr/sfdr vs. f sample , f in = 10.3 mhz 02874-a-013 encode (msps) db 70 75 80 65 60 55 50 5 15 25 35 45 55 65 ain = ?0.5dbfs 2v p-p sfdr (dbc) 1v p-p sfdr (dbc) 1v p-p snr (db) 2v p-p snr (db) figure 13 . ad9215 - 65 snr/sfdr vs. f sample , f in = 10.3 mhz 02874-a-066 55 60 65 70 75 80 85 0 100 80 60 40 20 db f sample (msps) 2v p-p sfdr 2v p-p snr figure 14 . ad9215 - 105 snr/sfdr vs. f sample , f in = 10.3 mhz
data sheet ad9215 rev. b | page 11 of 36 02874-a-014 analog input level db 40 50 60 70 80 30 20 10 0 ?50 ?40?45 ?35 ?25?30 ?10?15?20 ?5 0 2v p-p snr (db) 2v p-p sfdr (dbc) 1v p-p sfdr (dbc) 1v p-p snr (db) 80db reference line figure 1 5 . ad9215 - 80 snr/sfdr vs. analog input drive level, f sample = 80 msps, f in = 39.1 mhz 02874-a-067 0 80 70 60 50 40 30 20 10 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 db analog input level (?dbfs) 2v p-p snr 1v p-p snr 2 sfdr dbc 1v p-p sfdr (dbc) ?70dbfs reference line figure 16 . ad9215 - 105 snr/sfdr vs. analog input drive level, f sample = 105 msps, f in = 50.3 mhz 02874-a-015 analog input level db 40 50 60 70 80 30 20 10 0 ?50 ?40?45 ?35 ?25?30 ?10?15?20 ?5 0 2v p-p snr (db) 2v p-p sfdr (dbc) 1v p-p sfdr (dbc) 1v p-p snr (db) 80db reference line figure 17 . ad9215 - 65 snr/sfdr vs. analog input drive level, f sample = 65 msps, f in = 30.3 mhz 02874-a-072 50 55 60 65 70 75 80 0 50 100 150 200 250 300 sfdr snr db frequency (mhz) figure 18 . ad9215 - 105 snr/sfdr vs. f in , a in = ?0.5 db fs, f sample = 105 msps 02874-a-016 f in (mhz) db 50 55 60 65 70 75 80 85 0 100 50 150 250 200 300 2v p-p snr (db) 2v p-p sfdr (dbc) figure 19 . ad9215 - 80 snr/sfdr vs. f in , a in = ? 0.5 dbfs, f sample = 80 msps 02874-a-017 analog input (mhz) db 50 55 60 65 70 75 80 0 100 50 150 250 200 300 2v p-p snr (db) 2v p-p sfdr (dbc) figure 20 . ad9215 - 65 snr/sfdr vs. f in , a in = ? 0.5 dbfs, f sample = 65 msps
ad9215 data sheet rev. b | page 12 of 36 02874-a-060 frequency (mhz) db ?120 ?100 ?80 ?60 ?40 ?20 0 0 52.500 39.375 26.250 13.125 a in1 , a in2 = ?7dbfs sfdr = 74dbc figure 21. two-tone 32k fft with f in1 = 70.1 mhz, and f in2 = 71.1 mhz, f sample = 105 msps 02874-a-061 frequency (mhz) db ?120 ?100 ?80 ?60 ?40 ?20 0 0 52.500 39.375 26.250 13.125 a in1 , a in2 = ?7dbfs sfdr = 74dbc figure 22. two-tone 32k fft with f in1 = 100.3 mhz, and f in2 = 101.3 mhz, f sample = 105 msps 02874-a-068 0 80 70 60 50 40 30 20 10 ?65 ?55 ?45 ?35 ?25 ?15 ?5 db ain1, ain2 (dbfs) sfdr 80dbfs reference line figure 23. ad9215-105 two-tone sfdr vs. a in , f in1 = 70.1 mhz, and f in2 = 71.1 mhz, f sample = 105 msps 02874-a-073 0 80 70 60 50 40 30 20 10 ?60 ?5 ?10 ?15 ?20?25 ?30 ?35?40 ?45 ?50?55 db a in (dbfs) sfdr 80dbfs reference line figure 24. ad9215-80 two-tone sfdr vs. a in , f in1 = 100.3 mhz, and f in2 = 101.3 mhz, f sample = 105 msps 02874-a-069 30 80 75 70 65 60 55 50 45 40 35 20 30 40 50 60 70 80 db clock duty cycle high (%) sfdr dcs on sfdr dcs off snr dcs on snr dcs off figure 25. sinad, sfdr vs. clock duty cycle, f sample = 105 msps, f in = 50.3 mh 02874-a-070 50 55 60 65 70 75 80 ?40?200 20406080 dbc temperature ( ?c) 2v p-p sfdr (dbc) 1v p-p sfdr (dbc) 2v p-p sinad 1v p-p sinad figure 26. sinad, sfdr vs. temperature, f sample = 105 msps, f in = 50 mhz
data sheet ad9215 rev. b | page 13 of 36 02874-a-025 temperature (c) gain error (ppm/c) 10 20 30 0 40 ?40 ?30 ?20 ?10 ?40 ?20 0 20 60 40 80 figure 27 . gain vs. temperature externa l 1 v reference 02874-a-064 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 1024 896 768 640 512 384 256 1280 dnl (lsb) code figure 28 . ad9215 - 105 typical dnl, f sample = 105 msps, f in = 2.3 mhz 02874-a-074 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1024 896 768 640 512 384 256 1280 inl (lsb) code figure 29 . ad9215 - 105 typical inl, f sample = 105 msps, f in = 2.3 mhz
ad9215 data sheet rev. b | page 14 of 36 applying the ad9215 theory of operation the ad9215 architecture consists of a front - end sha followed by a pipelined switched capacitor adc. each stage provides sufficient overlap to correct for flash errors in the pr e ceding stages. the quantized outputs from each stage are co m bined into a fina l 10 - bit result in the digital correction logic. the pip e- lined architecture pe r mits the first stage to operate on a new input sample, while the remaining stages operate on pr e ceding samples. sampling o c curs on the rising edge of the clock. the input stage contains a differential sha that can be confi g- ured as ac - coupled or dc - coupled in differential or single - ended modes. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched capac i tor dac and interstag e residue amplifier (mdac). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pip e- line. redundancy is used in each one of the stages to facilitate digital correction of flash e rrors. the output - staging block aligns the data, carries out the error correction, and passes the data to the output buffers. the output buffers are powered from a separate supply, allowing adjus t- ment of the output voltage swing. during power - down, the out put buffers go into a high impedance state. analog input and reference overview the analog input to the ad9215 is a differential switched capacitor sha that has been designed for optimum perfo r- mance while processing a differential input signal. the sha in put can support a wide common - mode range and maintain excellent performance, as shown in figure 31 . an input co m- mon - mode voltage of midsupply minimize s sig nal - dependent er rors and provide s optimum performance. 02874-a-028 h h vin+ vin? c par c par t t 0.5pf 0.5pf t t figure 30 . switched - capacitor sha input the clock signal alternatively switches the sha between sa m ple mode and hold mode (see figure 30 ). when the sha is switched into sample mode, the signal source must be capable of cha rging the sample capacitors and settling within one - half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. also, a small shunt c a pa c itor can be plac ed across the inputs to provide dynamic charging currents. this passive network create s a low - pass filter at the adcs i n- put; therefore, the precise values are dependent upon the appl i- cation. in if undersampling applications, any shunt capac i tors should be removed. in combination with the driving source impedance, they would limit the input ban d width. the analog inputs of the ad9215 are not internally dc biased. in ac - coupled applications, the user must provide this bias e x- ternally. v cm = av d d /2 is recommen ded for optimum perfo r- mance, but the device function s over a wider range with re a- sonable performance (see figure 31). 02874-a-071 40 45 50 55 60 65 70 75 80 85 0.25 0.75 1.25 1.75 2.25 2.75 db analog input common-mode voltage (v) 2v p-p sfdr 2v p-p snr figure 31 . ad9215 - 105 snr, sfdr vs. common - mode voltage for best dynamic performance, the source impedances driving vin+ and vin? should be matched such that common - mode settling errors are symmetrical. these errors are reduced by the common - mode rejection of the adc. an internal differential reference buffer creates positive and negative reference voltages, reft and refb, respectively, that define the span of the adc core. the output common mode of the reference buffer is set to midsupply, and the reft and refb voltages and span are defined as reft = 1/2 ( av d d + vref ) refb = 1/2 ( av d d ? vre f ) span = 2 ( reft ? refb ) = 2 vref it can be seen from the equations above that the reft and refb voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the vref voltage. the internal voltage reference can be pin - strapped to fixed va l- ues of 0.5 v or 1.0 v or adjusted within the same range as di s- cussed in the internal reference connection section. maximum snr performance is achieved with the ad9215 set to the largest input span of 2 v p - p. the relative snr degradation is 3 db
data sheet ad9215 rev. b | page 15 of 36 when changing from 2 v p - p mode to 1 v p - p mode. the sha may be driven from a source that keeps the signal peaks within the allowable range for the selected reference vol t- age. the minimu m and maximum common - mode input levels are defined as vcm min = vref /2 vcm max = ( av d d + vref )/2 the minimum common - mode input level allows the ad9215 to accommodate ground - referenced inputs. although optimum performance is achieved with a differential inpu t, a single - ended source may be driven into vin+ or vin?. in this configuration, one input accept s the signal, while the op posite input should be set to midscale by connecting it to an appropriate reference. for example, a 2 v p - p signal may be applied to vin+ while a 1 v reference is applied to vin?. the ad9215 then accept s a signal varying between 2 v and 0 v. in the single - ended configuration, distortion performance may degrade significantly as compared to the differential case. ho w- ever, the effect is less noticeable at lower input fr e quencies. different ial input configurations as previously detailed, optimum performance is achieved while driving the ad9215 in a differential input configuration. for baseband applications, the ad8138 differential driver pr o vides excellent performance and a flexible interface to the adc. the output common - mode voltage of the ad8138 is easily set to av d d /2, and the driver can be configured in a sallen key filter topology to provide band limiting of the input signal. 02874-a-030 ad8138 ad9215 vin+ vin? avdd agnd 1v p-p r r c c 499? 499? 499? 523? 49.9? 1k? 1k? 0.1f v cm figure 32 . differential input configuration using the ad8138 at input frequencies in the second nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the ad9215. this is especially true in if un dersampling applications where frequen cies in the 70 mhz to 200 mhz range are being sampled. for these applications, diffe r- ential transformer coupling is the recommended input configur a- tion. the value of the shunt capacitor is depen d ant on the input frequency and source impedance and should be reduced or r e- moved. an e x ample of this is shown in figure 33 . 02874-a-031 ad9215 vin+ vin? avdd agnd 2v p-p r r c c 49.9? 0.1f avdd 1k? 1k? figure 33 . differential transformer - coupled configur ation the signal characteristics must be considered when selecting a tran sformer. most rf transformers s aturate at frequencies be low a few mhz, and excessive signal power can also cause core sat u ration, which leads to distortion. single - ended input configuration a single - ended input may provide adequate performance in cost - sen sitive applications. in this configuration, there is a de g- radation in sfdr and distortion performance due to the large input common - mode swing. however, if the source i m pedances on each input are kept matched, there should be little effect on snr performan ce. figure 34 details a typical single - ended input configuration. 02874-a-032 2v p-p r r c c 49.9? 0.1f 10f 10 f 0.1f ad9215 vin+ vin? avdd agnd avdd 1k? 1k? 1k? 1k? figure 34 . single - ended input configuration clock input and cons iderations typical high speed adcs use both clock edges to ge n erate a vari ety of internal timing signals, and as a result may be sens i- tive to clock duty cycle. commonly, a 5% tolerance is r e quired on the clock duty cycle to maintain dynamic performance cha r- acteristics. the ad9215 contains a clock duty cycle stabilizer that retim es the nonsampling edge, providing an i n ternal clock signal with a nominal 50% duty cycle. this allows a wide range of clock input duty cycles without affecting the perfor m ance of the ad9215. as shown in figure 25 , noise and distortion pe r- formance are nearly flat over a 50% range of duty c ycle. for best ac performance, enabling the duty cycle stabilizer is reco m- mended for all applications. the duty cycle stabilizer uses a delay - locked loop (dll) to cr e- ate the nonsampling edge. as a result, any changes to the sa m- pling frequency require approximately 100 clock c y cles to allow the dll to acquire and lock to the new rate.
ad9215 data sheet rev. b | page 16 of 36 table 7 . reference configuration summary selected mode external sense connection inter nal op amp configuration resulting vref (v) resulting differential span (v p - p) externally supplied reference avdd n/a n/a 2 external reference internal 0.5 v reference vref voltage follower (g = 1) 0.5 1.0 programmed variable reference ext ernal divider noninverting (1 < g < 2) 0.5 (1 + r2 / r1 ) 2 vref internally programmed 1 v reference agnd to 0.2 v internal divider 1.0 2.0 table 8 . digital output coding code vin+ ? vin? input span = 2 v p - p (v) vin+ ? vin? input span = 1 v p - p (v) digital output offset binary (d9??????d0) digital output twos complement (d9??????d0) 1023 1.000 0.500 11 1111 1111 01 1111 1111 512 0 0 10 0000 0000 00 0000 0000 511 ?0.00195 ?0.000978 01 1111 1111 11 1111 1111 0 ?1.00 ?0.5000 00 0000 0000 10 0000 0000 high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given full -scale input frequency (f input ) due only to aperture jitter (t a ) can be cal culated with the following equation snr degradation = 20 log 10 [2 f input t a ] in the equation, the rms aperture jitter, t a , represents the root - sum square of all jitter sources, which include the clock input, analog input signal, and adc aperture jitter specification. un dersampling applications are particularly sensitive to jitter. the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9215. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal - controlled oscillators make the best clock sources. if the clock is gene r ated from another type of source (by gating, dividing, o r other methods), it should be retimed by the original clock at the last step. power dissipation and standby mode as shown in figure 35 , the power dissipated by the ad9215 is proportional to its sample rate. the digital power dissi pation does not vary substantially between the three speed grades be cause it is determined primarily by the strength of the digital drivers and the load on each output bit. the maximum drvdd current can be calculated as i drvdd = v drvdd c load f clock n where n is the number of output bits, 10 in the case of the ad9215. this maximum current is for the condition of every output bit switching on every clock cycle, which can only occur for a full - scale square wave at the nyquist frequency, f clock /2. in pra ctice, the drvdd current is established by the average number of output bits switching, which are determined by the encode rate and the characteristics of the analog input si g nal. digital power consumption can be minimized by reducing the capacitive load p resented to the output drivers. the data in fi g- ure 35 was taken with a 5 pf load on each ou t put driver. 02874-a-075 15 35 30 25 20 40 105 5 15 25 35 45 55 65 75 85 95 i avdd (ma) i drvdd ?1 1 3 5 7 9 11 13 15 f sample (msps) ad9215-105 i avdd ad9215-65/80 i avdd i drvdd figure 35 . supply current vs. f sample for f in = 10.3 mhz the analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. each speed grade dissipates a baseline power at low sample rates that increases linearly with the clock frequency. by asserting the pdwn pin high, the ad9215 i s placed in standby mode. in this state, the adc typically dissipate s 1 mw if the clk and analog inputs are static. during standby, the output drivers are placed in a high impedance state. rea s serting the pdwn pin low returns the ad9215 into its normal ope r a- tional mode. in standby mode, low power dissipation is achieved by shutting down the reference, reference buffer, and biasing networks. the
data sheet ad9215 rev. b | page 17 of 36 decoupling capacitors on reft and refb are discharged when entering standby mode and then must be recharged when returning to normal operation. as a result, the wake-up time is related to the time spent in standby mode, and shorter standby cycles result in proportionally shorter wake-up times. with the recommended 0.1 f and 10 f decoupling capacitors on reft and refb, it takes approximately one second to fully discharge the reference buffer decoupling capacitors and 7 ms to restore full operation. digital outputs the ad9215 output drivers can be configured to interface with 2.5 v or 3.3 v logic families by matching drvdd to the digital supply of the interfaced logic. the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. however, large drive currents tend to cause current glitches on the supplies that may affect converter performance. applications requiring the adc to drive large capacitive loads or large fanouts may require external buffers or latches. timing the ad9215 provides latched data outputs with a pipeline delay of five clock cycles. data outputs are available one propagation delay (t od ) after the rising edge of the clock signal. refer to fig- ure 2 for a detailed timing diagram. the length of the output data lines and loads placed on them should be minimized to reduce transients within the ad9215; these transients can detract from the converters dynamic per- formance. the lowest typical conversion rate of the ad9215 is 5 msps. at clock rates below 5 msps, dynamic performance may degrade. voltage reference a stable and accurate 0.5 v voltage reference is built into the ad9215. the input range can be adjusted by varying the refer- ence voltage applied to the ad9215, using either the internal reference or an externally applied reference voltage. the input span of the adc tracks reference voltage changes linearly. max- imum snr and dnl performance is achieved with the ad9215 set to the largest input span of 2 v p-p. internal reference connection a comparator within the ad9215 detects the potential at the sense pin and configures the reference into four possible states, which are summarized in table 1 . if sense is grounded, the reference amplifier switch is connected to the internal resis- tor divider (see figure 36), setting vref to 1 v. connecting the sense pin to the vref pin switches the amplifier output to the sense pin, configuring the internal op amp circuit as a voltage follower and providing a 0.5 v reference output. if an external resistor divider is connected as shown in figure 37, the switch is again set to the sense pin. this puts the reference amplifier in a noninverting mode with the vref output defined as ? ? ? ? ? ? ??? r1 r2 vref 15. 0 02874-a-034 10 ? f + 0.1? f vref sense 0.5v 7k ? 7k ? ad9215 vin? vin+ reft 0.1? f 0.1? f 10 ? f 0.1? f refb select logic adc core figure 36. internal reference configuration in all reference configurations, reft and refb drive the adc conversion core and establish its input span. the input range of the adc always equals twice the voltage at the reference pin for either an internal or an external reference. 02874-a-035 10? f + 0.1 ? f vref r2 r1 sense 0.5v ad9215 vin? vin+ reft 0.1 ? f 0.1 ? f 10? f 0.1 ? f refb select logic adc core figure 37. programmable reference configuration if the internal reference of the ad9215 is used to drive multiple converters to improve gain matching, the loading of the refer- ence by the other converters must be considered. figure 38 de- picts how the internal reference voltage is affected by loading.
ad9215 data sheet rev. b | page 18 of 36 02874-a-036 i load (ma) vref error (%) 0 0.05 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.5 1.0 1.5 2.0 2.5 3.0 vref = 0.5v vref = 1.0v figure 38 . vref accuracy vs. load external reference operation the use of an external reference may be necessary to enhance the gai n accuracy of the adc or improve thermal drift chara c- teristics. when multiple adcs track one another, a single refe r- ence (internal or external) may be necessary to reduce gain matching errors to an acceptable level. a high precision exte r nal reference may also be selected to provide lower gain and offset temperature drift. figure 39 shows the typical drift characteri s- tics of the internal reference in both 1 v and 0.5 v modes. 02874-a-037 temperature ( c) vref error (%) 0.4 0.5 0.6 0.3 0.2 0.1 0 ?40 ?20 0 20 40 60 80 vref = 1.0v vref = 0.5v figure 39 . typ ical vref drift when the sense pin is tied to avdd, the internal reference is disabled, allowing the use of an external reference. an internal reference buffer load s the external reference with an equiv a lent 7 k? load. the internal buffer still generate s t he positive and negative full - scale references, reft and refb, for the adc core. the input span is always twice the value of the refe r ence voltage; therefore, the external refe r ence must be limited to a maximum of 1 v. operational mode selection as discus sed earlier, the ad9215 can output data in either of f set binary or twos complement format. there is also a provision for enabling or disabling the clock duty cycle stabilizer (dcs). the mode pin is a multilevel input that controls the data fo r mat and dcs s tate. for best ac performance, enabling the duty cycle stabilizer is recommended for all applications. the input threshold values and corresponding mode selections are ou t- lined in table 9 . as detailed in tab le 9 , the data format can be selected for either offset binary or twos complement. table 9 . mode selection mode voltage data format duty cycle stabilizer avdd twos complement disabled 2/3 avdd twos complement enabled 1/ 3 avdd offset binary enabled agnd (default) offset binary disabled the mode pin is internally pulled down to agnd by a 20 k? resistor. evaluation board the ad9215 evaluation board is no longer in production. the following evaluation board documenta tion is provided for i n- formational purposes only. the ad9215 evaluation board provides all of the support ci r- cuitry required to operate the adc in its var i ous modes and configurations. the converter can be driven differentially through an ad8351 driver, a transformer, or single - ended. se p- arate power pins are provided to isolate the dut from the su p- port circuitry. each input configuration can be selected by proper connection of various jumpers (refer to the schematics). figure 40 sho ws the typical bench characteriz a tion setup used to evaluate the ac perfo r mance of the ad9215. it is critical that signal sources with very low phase noise (<1 ps rms jitter) be used to realize the ultimate performance of the converter. pro p- er filtering of the input signal, to remove ha r monics and lower the integrated noise at the input, is also ne c essary to achieve the specified noise perfo r mance. complete schematics and layout plots follow that demo n strate the proper routing and grounding techniques that should be applied at the system level. 02874-a-038 r and s smg, 2v p-p signal synthesizer r and s smg, 2v p-p signal synthesizer refin 10mhz refout band-pass filter 3.0v ? + ? + ? + ? + 2.5v 5.0v avdd drvdd gnd gnd v dl vamp xfmr input clk p12 ad9215 evaluation board data capture and processing 2.5v figure 40 . evaluation board connections
data sheet ad9215 rev. b | page 19 of 36 02874-a-039 29 1 2 3 4 5 6 p13 p14 xfrin1 optional xfr t2 ft c1?1?13 nc ct 1 t1 adt1?1wt 6 2 3 4 5 1 2 3 4 5 r single ended r18 25? r3, r17, r18 only one should be on board at a time extref 1v max e1 r1 10k? r9 10k? 0.1f c12 c9 0.10f gnd gnd gnd gnd gnd avdd c29 10f c11 0.1f c7 0.1f gnd gnd avdd p7 a b c d p9 p8 p11 p10 e c13 0.10f c22 10f p6 p1 p3 p4 1 2 3 4 gnd gnd c8 0.1f p5 2 mode 25 26 27 28 30 31 32 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 refb reft agnd vin+ agnd avdd avdd vin? ad9215 u4 vref sense mode d9 or d8 d7 d6 drvdd dgnd d5 d3 d4 d2 d1 d0 16 15 14 13 12 11 10 9 dnc clk dnc dnc dnc dnc dnc pdwn (lsb) drvdd gnd 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 orx d13x d12x d10x d11x d9x d8x d7x d6x d5x d4x d2x d3x d1x d0x (msb) overrange bit avdd gnd drvdd vdl gnd vamp p2 gnd h1 mthole6 h2 mthole6 h3 mthole6 h4 mthole6 3.0v 2.5v 2.5v 5.0v rp2 220? rp1 220? sense pin solderable jumper: e to a: external voltage divider e to b: internal 1v reference (default) e to c: external reference e to d: internal 0.5v reference mode pin solderable jumper: 5 to 1: twos complement/dcs off 5 to 2: twos complement/dcs on 5 to 3: offset binary/dcs on 5 to 4: offset binary/dcs off gnd r8 1k? clk avdd gnd r25 1k? r13 1k? r15 33? avdd gnd gnd gnd c19 10pf or l1 for filter gnd avdd r4 33? r36 1k? ? r26 1k? gnd avdd avdd gnd gnd vin+ vin? c21 select c23 select r2 xx r10 36? r12 0? ampin x out gnd x out b r3 0? r11 36? c5 0.1f c26 10pf e 45 c16 0.1f r42 0? c6 0.1f gnd gnd amp ampinb c15 0.1f l1 100 gnd pri sec pri sec gnd c18 0.10f x frin x out b ct x out j1 r5 1k? r7 1k? r6 1k? figure 41 . lfcsp evaluation board schematic, analog inputs and dut
ad9215 data sheet rev. b | page 20 of 36 02874-a-040 drx d13x gnd d2x d1x gnd d0x d11x d12x drvdd d10x d9x gnd d8x d7x d5x d6x gnd d4x d3x drvdd 2clk 2db 2d7 gnd 2d6 2d5 1d2 1d1 1clk 1 2d4 v cc 2d3 gnd 2d2 2d1 1d7 1d6 1d5 1d8 gnd 1d4 1d3 gnd 2oe 2qb 2q7 2q6 2q5 1q2 1q1 1oe 2q4 2q3 gnd gnd 2q2 2q1 1q8 1q7 1q5 gnd v cc v cc v cc 1q6 1q4 1q3 gnd 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 in out clkat/dac u1 74lvth162374 clklat/dac gnd gnd drvdd gnd gnd drvdd gnd gnd dry msb lsb 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 gnd dr gnd msb dry gnd ampin ampinb gnd vamp gnd gnd gnd gnd vamp gnd gnd vamp gnd p12 header 40 c27 0.1f c45 0.1f c28 0.1f c35 0.10f c24 10f c17 0.1f r16 0? r14 25? r40 10k? pwdn 1 rgp1 2 inhi 3 inlo 4 rpg2 5 r41 10k? r35 25? r33 25? r34 1.2k? r19 50? amp in amp r17 0? r38 1k? r39 1k? u3 ad8351 power down use r40 or r41 c44 0.1f gnd 6 comm 7 oplo 8 ophi 9 vpos 10 vocm figure 42 . lfcsp evaluation board, digital path
data sheet ad9215 rev. b | page 21 of 36 02874-a-041 c10 22f c4 10f c3 10f c25 10f c32 0.001f c33 0.1f c14 0.001f vdl drvdd avdd gnd gnd avdd dut bypassing clock timing adjustments for a buffered encode use r28 for a direct encode use r27 analog bypassing digital bypassing gnd drvdd c41 0.1f c2 22f c30 0.001f c31 0.1f c46 10f c34 0.1f c36 0.1f c38 0.001f c1 0.1f c47 0.1f c48 0.001f c49 0.001f c20 10f c37 0.1f c40 0.001f gnd gnd vamp vdl c39 0.001f encx clk enc encode r27 0? r32 1k? r23 0? r37 25? r22 0? rx dnp r28 0? e50 e51 enc vdl vdl vdl e52 e53 e31 e35 e43 e44 gnd gnd gnd pwr gnd clklat/dac vdl gnd vdl gnd c43 0.1f r31 1k? r20 1k? r21 1k? r24 1k? r30 1k? r29 50? gnd j2 gnd vdl gnd 1 1y u5 2y 3y 4y 2 4 5 9 10 3 6 7 8 11 14 12 13 74vcx86 encx 1b 1a 2b 2a 3b 3a 4b 4a dr schematic shows two-gate delay setup. for one delay remove r22 and r37 attach rx (rx = 0?) latch bypassing figure 43 . lfcsp evaluation board schematic, clock input
ad9215 data sheet rev. b | page 22 of 36 02874-a-042 figure 44 . lfcsp evaluation board layout, primary side 02874-a-043 figure 45 . lfcsp evaluation board layout , secondary side
data sheet ad9215 rev. b | page 23 of 36 02874-a-044 figure 46 . lfcsp evaluation board layout, ground plane 02874-a-045 figure 47 . lfcsp evaluation board layout, power plane
ad9215 data sheet rev. b | page 24 of 36 02874-a-046 figure 48 . lfcsp evaluation board layout, primary silkscreen 02874-a-047 figure 49 . lfcsp evaluation board layout, secondary silkscreen
data sheet ad9215 rev. b | page 25 of 36 table 10. lfcsp evaluation board bill of materials (bom) item qty omit 1 reference designator device package value recommended vendor/ part number 1 18 c1, c5, c7, c8, c9, c11, c12, c13, c15, c16, c31, c33, c34, c36, c37, c41, c43, c47 chip capacitor 0603 0.1 f 8 c6, c18, c27, c17, c28, c35, c45, c44 2 8 c2, c3, c4, c10, c20, c22, c25, c29 tantalum capacitor tajd 10 f 2 c46, c24, 3 8 c14, c30, c32, c38, c39 c40, c48, c49 chip capacitor 0603 0.001 f 4 1 c19 chip capacitor 0603 10 pf 2 c21, c23 5 1 c26 chip capacitor 0603 10 pf 6 9 e31, e35, e43, e44, e50, e51, e52, e53 header ehole jumper blocks 2 e1, e45 7 2 j1, j2 sma connector/50 sma 8 1 l1 inductor 0603 10 nh coilcraft/0603cs- 10nxgbu 9 1 p2 terminal block tb6 wieland/25.602.2653.0 z5-530-0625-0 10 1 p12 header dual 20-pin rt angle header40 digi-key s2131-20-nd 11 5 r3, r12, r23, r18, rx chip resistor 0603 0 6 r37, r22, r42, r16, r17, r27 12 2 r4, r15 chip resistor 0603 33 13 14 r5, r6, r7, r8, r13, r20, r21, r24, r25, r26, r30, r31, r32, r36 chip resistor 0603 1 14 2 r10, r11 chip resistor 0603 36 15 1 r29 chip resistor 0603 50 1 r19 16 2 rp1, rr2 resistor pack r_742 220 digi-key cts/742c163220jtr 17 1 t1 adt1-1wt awt1-t1 mini-circuits 18 1 u1 74lvth162374 cmos register tssop-48 19 1 u4 ad9215bcp adc (dut) csp-32 analog devices, inc. 20 1 u5 74vcx86m soic-14 fairchild 21 1 pcb ad9xxbcp/pcb pcb analog devices, inc. 22 1 u3 ad8351 op amp msop-8 analog devices, inc. 23 1 t2 macom transformer etc1-1-13 1-1 tx macom/etc1-1-13 24 5 r9, r1, r2, r38, r39 chip resistor 0603 select 25 3 r18, r14, r35 chip resistor 0603 25 26 2 r40, r41 chip resistor 0603 10 k 27 1 r34 chip resistor 1.2 k 28 1 r33 chip resistor 110 1 these items are included in the pcb design but are omitted at assembly.
ad9215 data sheet rev. b | page 26 of 36 02874-a-048 orx d5x d6x d7x d8x d9x + + agnd vin+ avdd clk mode or pwdn refb reft sense vref vin? agnd avdd d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 drgnd drvdd dnc dnc pri sec cd b a mode select f g e h mode select configuration e:2c/dcs off f:2c/dcs on g:ob/dcs on h:ob/dcs off (lsb) (msb) optional optional differential input analog input options 1. r6, r34 for differential operation 2. c1, c33 for op amp operation 3. r7, r46, r5, c9, c23 for single-ended operation common mode please jumper e45 to e32 dc voltage adjust or jumper e45 to e12 capacitor to ground overrange bit e9 e11 gnd gnd avdd ain ain amp j1 l1 10nh gnd avdd e19 e16 e17 sense gnd vref or1 8 9 7 13 2 1 14 5 6 3 4 10 11 12 17 18 19 20 21 22 25 26 27 28 23 24 16 15 device = ad9215 u1 parts = 1 c29 10? f ampin ampin gnd gnd gnd gnd avdd gnd avdd 1 5 34 2 6 t1 gnd gnd 9 10 12 13 14 15 2 3 4 5 6 7 8 1 16 11 clk gnd gnd e7 e8 e2 e5 e21 e20 e18 e22 e23 avdd e1 e3 e4 e6 2 3 4 5 6 7 8 1 9 10 12 13 14 15 16 11 e45 e12 com gnd 3.0v 5.0v 2.5v 3.0v 3.0v vdl 13 24 p2 13 24 vamp gnd vclk gnd gnd drvdd avdd avdd gnd gnd drvdd gnd ncx d4x d3x d2x d1x d0x nc2x gnd avdd gnd gnd gnd drvdd vdl e29 e28 e27 e26 e25 e24 vclk avdd gnd gnd reference configuration a: external voltage divider reference b: internal 1v reference c: external reference d: internal 0.5v reference 1v max single-ended input operation 1. place r7( 50 ? ), r5( 0 ? ) and r46 (25 ? ) 2. place c23 (0.1 ? f), c9 (0.1 ? f) 3. remove c33, c1, r34, r6, c32 rp2 220 ? rp1 220 ? r11 1k? r29 1k? r24 1k? r21 33? r19 33? r44 1k ? r45 1k? r34 0 ? r6 0 ? r25 25? r32 36? r33 36? r5 0 ? r16 xx r8 1k? r10 1k? r9 1k? r4 10k ? r15 10k ? r7 50? c32 0.1? f c7 0.001? f c9 0.1 ? f c6 0.1? f c16 0.1? f c13 0.1? f c15 0.1? f optional e32 gnd avdd gnd gnd r3 5k? r1 10 ? c14 0.1? f c12 0.1? f c23 0.1 ? f c11 0.1? f c5 10pf c8 10pf c18 0.1? f c30 0.1? f c52 10? f c17 0.1 ? f figure 50. tssopp evaluation board schematic, analog inputs and dut
data sheet ad9215 rev. b | page 27 of 36 cp y7 y6 y5 y4 y3 y2 y1 y0 vcc gnd x7 x6 x5 x4 x3 x2 x1 x0 oe cp y7 y6 y5 y4 y3 y2 y1 y0 vcc gnd x7 x6 x5 x4 x3 x2 x1 x0 oe p2 p4 p6 p8 p10 p12 p14 p16 p18 p20 p22 p24 p26 p28 p1 p3 p5 p7 p9 p11 p13 p15 p17 p19 p21 p23 p25 p27 p30 p29 p32 p31 p34 p33 p35 p38 p37 p40 p39 p36 msb msb lsb out of range bit strap this at assembly u2 11 12 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 1 u3 74lvt574 device = 74lvt574a 9 10 12 13 14 15 2 3 4 5 6 7 8 1 16 11 rp4 220? clklat/dac clklat/dac gnd gnd gnd gnd 9 10 12 13 14 15 2 3 4 5 6 7 8 1 16 11 rp3 220 ? ncx gnd d4x d3x d2x d1x d0x vdl gnd vdl 11 10 20 2 3 4 5 6 7 8 9 19 18 17 16 15 14 13 12 1 u4 74lvt574 device = 74lvt574a vdl e30 e14 gnd drx gnd gnd gnd gnd d5x d6x d7x d8x d9x orx gnd gnd nc2x gnd gnd gnd e13 gnd rgp2 inlo inhi rgp1 pwup vamp 5 4 3 2 1 vamp gnd comm oplo ophi vpos vocm + gnd gnd 6 7 8 9 10 u6 device = ad8351 vamp gnd gnd amp r31 100 ? r51 25? r50 25? r49 1k? r48 1k? r27 0? r17 0? r30 1.2k? r36 25? r20 150? r22 10k? r47 10k ? r28 0? r23 100? c45 0.1f c44 0.1f c31 10pf c41 0.1f c42 0.1f c33 0.1f c1 0.1f c43 0.001f ampin ampin c47 10f 02874-a-049 figure 51 . tssop evaluation board, digital path
ad9215 data sheet rev. b | page 28 of 36 02874-a-050 + c27 10 ? f + c25 10 ? f c24 0.1 ? f c26 0.1 ? f c37 0.001 ? f c38 0.001 ? f vdl gnd u3/u4 bypassing + c20 10 ? f c36 0.1 ? f c39 0.001 ? f vclk gnd u5 bypassing avdd bypassing gnd avdd c48 0.1 ? f c34 0.1 ? f c35 0.001 ? f c49 0.001 ? f c51 0.1 ? f + c50 10 ? f gnd gnd dut bypassing vclk + c2 22 ? f vdl + c10 22 ? f drvdd + c4 10 ? f avdd + c3 22 ? f c46 0.1 ? f drvdd gnd dut drvdd bypassing c21 0.1 ? f c19 0.001 ? f 1a 1b 1y 2a 2b 2y 3a 3b 3y 4a 4b 4y pwr gnd encode schematic shows 1-gate delay setup for two-gate delay remove resistor r52 add resistors r38 and r18 optional external data ready vclk drx drx drx encx 1 2 3 4 5 6 9 10 8 12 13 11 14 7 u5 74vcx86 clklat/dac j3 gnd e52 e53 gnd gnd gnd avdd e51e50 gnd e44e43 vclk gnd vclk encx enc clk gnd vclk e36e35 gnd enc vclk j4 gnd gnd encode from xor for a buffered encode use r37 for a direct encode use r35 r40 50 ? r41 1k ? r42 1k ? r39 1k ? r26 1k ? r2 1k ? r43 1k ? r52 0 ? r38 0 ? r18 0 ? r25 0 ? r35 0 ? r37 0 ? r14 50? c40 0.1 ? f c28 0.1 ? f figure 52. tssop evaluation board schematic, clock input
data sheet ad9215 rev. b | page 29 of 36 02874-a-051 figure 53 . tssop evaluation board layout, primary side 02874-a-052 figure 54 . tssop evaluation board layout, secondary side 02874-a-053 figure 55 . tssop evaluation board layout, ground plane 02874-a-054 figure 56 . tssop evaluation board layout, power plane
ad9215 data sheet rev. b | page 30 of 36 02874-a-055 figure 57 . tssop e valuation board layout, primary silkscreen 02874-a-056 figure 58 . tssop evaluation board layout, secondary silkscreen
data sheet ad9215 rev. b | page 31 of 36 table 11. tssop evaluation board bill of materials (bom) item qty. omit reference designator device package value recommended vendor/part no. 1 11 c2 to c4, c10, c20, c25, c27, c29, c47, c50, c52 tantalum capacitor tajd 10 f c47 2 2 c5,c8 chip capacitor 0603 10 pf 1 c31 3 15 c6, c9, c13, c15 to c18, c21, c24, c26, c30, c32, c34, c36, c40, c46, c48, c51 chip capacitor 0603 0.1 f 4 3 c12, c14, c23, c28 chip capacitor 0603 select 5 8 c7, c19, c35, c19, c37 to c39, c49 chip capacitor 0603 0.001 f 6 6 c1,c33, c41 to c42, c44 to c5 bcap0402 0402 0.1 f 7 1 c43 bcap0402 0402 0.001 f 8 1 c11 bcap0603 0603 select 9 11 r2, r8 to r11, r24, r26, r29, r39, r41 to r45 bres603 0603a 1 k 2 r48, r49 10 4 r6, r25, r34, r37 bres603 0603a 0 8 r5, r35, r17 to r18, r27 to r28, r38, r52 11 2 r7, r40 bres603 0603a 50 1 r14 12 2 r19, r21 bres603 0603a 33 13 2 r32, r33 res0603 0603a 36 14 1 r16 bres603 0603 select 15 2 r4, r15, bres603 0603 10 k 16 4 r20, r22 to r23, r47 bres603 0603a select 17 2 r48, r49 bres603 0603 1 k 18 4 r36, r46, r50 to r51 bres603 0603 25 19 1 r31 bres603 0603 100 20 1 r30 bres603 0603 1.2 k 21 1 r3 bres603 0603 5 k 22 1 r1 potentiometer rj24fw 10 k 23 4 rp1 to rp4 resister pack 220 742c163221
ad9215 data sheet rev. b | page 32 of 36 item qty. omit r eference designator device package value recommended vendor/part no. 24 1 l1 chip inductor 0603 10 nh coilcraft/0603cs - 10nxgbu 25 1 t1 1:1 rf transformer cd542 mini - circuits awt1 -1t 26 1 u1 adc 28tssop analog devi ces , inc. ad9215 27 1 u2 right angle 40 - pin header samtec tsw - 120-08 -t-d- ra 28 2 u3, u4 octal d - type flip - flop fairchild 74lvt57 msa 29 1 u5 quad xor gate so14 fairchild 74vcx86 m 30 1 u6 high speed amplifier somb10 analog devices , inc. ad8351 arm 31 2 j1, j3 smb connecter smbp 1 j4 32 2 p1, p2 power connector ptmicro4 weiland z5.531.3425.0 posts 25.602.5453.0 top 33 26 e1/e5, e2/e3, e4/e8, e9/e11, e6/e7, e16/e17, e19/e22, e18/e23, e21/20, e35/e51, e36/e50, e43/e53, e44/e52 he aders/jumper blocks tsw - 120-07 -g-s smt - 100-bk -g 34 12 e24/e27, e25/e26, e28/e29, e13/e14/e30, e12/e32/e45 wirehole
data sheet ad9215 rev. b | page 33 of 36 outline dimensions compliant to jedec standards mo-153-ae 28 15 14 1 8 0 seating plane c oplanarit y 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 figure 59. 28-lead thin shrink small outline package [tssop] (ru-28) dimensions shown in millimeters compliant to jedec standards mo-220-whhd. 112408-a 1 0.50 bsc bottom view top view pin 1 indicator 32 9 16 17 24 25 8 exposed pad p i n 1 i n d i c a t o r 3.25 3.10 sq 2.95 s eating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min figure 60. 32-lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp-32-7) dimensions shown in millimeters
ad9215 data sheet rev. b | page 34 of 36 ordering guide model 1 temperature range package description pac kage option ad9215bruz - 65 ?40c to +85c 28- lead thin shrink small outline package (tssop) ru -28 ad9215bruz - 80 ?40c to +85c 28- lead thin shrink small outline package (tssop) ru -28 ad9215bruz - 105 ?40c to +85c 28- lead thin shrink small outl ine package (tssop) ru -28 ad9215bruzrl7 - 65 ?40c to +85c 28- lead thin shrink small outline package (tssop) ru -28 ad9215bruzrl7 - 80 ?40c to +85c 28- lead thin shrink small outline package (tssop) ru -28 ad9215bruzrl7 - 105 ?40c to +85c 28- lead t hin shrink small outline package (tssop) ru -28 ad9215bcpz -65 ?40c to +85c 32- lead lead frame chip scale package (lfcsp _wq ) cp -32 -7 ad9215bcpz -80 ?40c to +85c 32- lead lead frame chip scale package (lfcsp _wq ) cp -32 -7 ad9215bcpz - 105 ?40c to +85c 32- lead lead frame chip scale package (lfcsp _wq ) cp -32 -7 1 z = rohs compliant part.
data sheet ad9215 rev. b | page 35 of 36 notes
ad9215 data sheet rev. b | page 36 of 36 notes ? 200 3C 2013 analog devices, inc. all rights reserved. trademarks and regi s tered trademarks are the property of their respective owners. d 02874 -0-2 /13 (b)

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